NBTI-aware technique for transistor sizing of high-performance CMOS gates.
Maurício Banaszeski da SilvaVinicius V. A. CamargoLucas BrusamarelloGilson I. WirthRoberto da SilvaPublished in: LATW (2009)
Keyphrases
- high speed
- low power
- logic circuits
- power dissipation
- circuit design
- power consumption
- low power consumption
- low cost
- metal oxide semiconductor
- single chip
- image sensor
- integrated circuit
- analog vlsi
- cost effective
- cmos image sensor
- data intensive
- cmos technology
- scientific computing
- genetic algorithm
- parallel processing
- power supply
- general purpose
- information systems
- vlsi circuits
- floating gate
- learning algorithm
- data sets
- power losses