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Gate Sizing for Power-Delay Optimization at Transistor-level Monolithic 3D-Integrated Circuits.
Juliano C. Zanelli
Carolina Metzler
Ricardo Augusto da Luz Reis
Published in:
LASCAS (2020)
Keyphrases
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integrated circuit
power losses
metal oxide semiconductor
electron beam
optimization algorithm
global optimization
high speed
power consumption
power transmission
neural network
image processing
optimization method
constrained optimization
levels of abstraction