Aging resilient RO PUF with increased reliability in FPGA.
Sreeja ChowdhuryXiaolin XuMark M. TehranipoorDomenic FortePublished in: ReConFig (2017)
Keyphrases
- software aging
- signal processing
- hardware implementation
- high speed
- real time image processing
- electronic devices
- reliability analysis
- data acquisition
- application server
- low cost
- field programmable gate array
- reliability assessment
- single chip
- case study
- neural network
- real time
- hardware design
- video sequences
- highly reliable
- hardware architecture
- age estimation
- image processing
- computer vision
- social networks
- fpga implementation
- information retrieval