On the Impact of Structural Circuit Partitioning on SAT-Based Combinational Circuit Verification.

Marc Herbstritt Thomas Kmieciak Bernd Becker

Published in: MTV (2004)

Keyphrases

high speed
asynchronous circuits
logic circuits
analog circuits
circuit design
tunnel diode
bounded model checking
duty cycle
active learning
neural network
evolutionary algorithm
frequency response
delay insensitive
semiconductor devices