The IBM z13 processor cache subsystem.
Craig R. WaltersPak-kin MakD. P. D. BergerMichael A. BlakeTim BronsonK. D. KlapprothA. J. O'NeillRobert J. SonnelitterVesselina K. PapazovaPublished in: IBM J. Res. Dev. (2015)
Keyphrases
- memory subsystem
- ibm zenterprise
- dynamic random access memory
- instruction set
- input output
- processor core
- embedded processors
- cache misses
- shared memory multiprocessors
- industry standard
- memory hierarchy
- database workloads
- memory access
- high speed
- floating point unit
- shared memory multiprocessor
- single chip
- parallel processing
- cache management
- computing power
- silicon on insulator
- operating system
- response time