Cache: Reliability-aware reconfigurable last-level cache architecture for multi-cores.
Florian KriebelArun SubramaniyanSemeen RehmanSegnon Jean Bruno AhandagbeMuhammad ShafiqueJörg HenkelPublished in: CODES+ISSS (2015)
Keyphrases
- memory hierarchy
- prefetching
- data access
- memory access
- query processing
- low cost
- hit rate
- general purpose
- main memory
- caching scheme
- management system
- memory subsystem
- multithreading
- memory management
- back end
- software architecture
- resource consumption
- hardware implementation
- cache misses
- dynamic random access memory
- multi core processors
- cache management
- processor core
- systolic array