Design and CAD methodologies for low power gate-level monolithic 3D ICs.
Shreepad A. PanthKambiz SamadiYang DuSung Kyu LimPublished in: ISLPED (2014)
Keyphrases
- low power
- cmos technology
- power consumption
- low cost
- logic circuits
- single chip
- high speed
- vlsi architecture
- low power consumption
- gate array
- digital signal processing
- nm technology
- computer aided
- design process
- mixed signal
- computer aided design
- power dissipation
- vlsi circuits
- ultra low power
- high power
- vlsi implementation
- cmos image sensor
- parallel processing
- embedded systems