FPGA Realization of Lane Detection Unit using Sliding-based Parallel-Segment Detection for Buffer Memory Reduction.
Heuijee YunDaejin ParkPublished in: ICCE (2023)
Keyphrases
- parallel hardware
- lane detection
- hough transform
- driver assistance systems
- lane markings
- lane departure
- detection method
- level parallelism
- image processing
- feature detection
- real time
- processing units
- memory access
- detection algorithm
- shared memory
- field programmable gate array
- edge detector
- event detection
- moving objects