High-Level Hierachical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules.
R. Bruce MaunderZoran A. SalcicGeorge G. CoghillPublished in: FPL (1999)
Keyphrases
- high level
- logic synthesis
- hardware design
- low level
- analog circuits
- delay insensitive
- functional modules
- program synthesis
- high speed
- design methodology
- asynchronous communication
- low level features
- data sets
- modular structure
- higher level
- source code
- analog vlsi
- tunnel diode
- modular architecture
- object level
- logic circuits
- quantum computing
- functional programs
- asynchronous circuits
- digital circuits
- texture synthesis
- data flow
- hardware implementation
- semantic information
- programming language
- circuit design
- knowledge structures
- heuristic search
- building blocks
- general purpose
- image processing