A 1.16mW 69dB SNR (1.2MHz BW) continuous time £Δ ADC with immunity to clock jitter.
Ganesh K. BalachandranVenkatesh SrinivasanVijay RentalaSrinath RamaswamyPublished in: CICC (2010)
Keyphrases
- power consumption
- high speed
- clock frequency
- signal to noise ratio
- low power
- cmos technology
- fpga device
- markov processes
- markov chain
- noise reduction
- packet loss
- optimal control
- database
- dynamical systems
- duty cycle
- multi objective optimization
- iterative learning control
- state space
- signal noise ratio
- hd video
- sampling rate
- power supply
- frame rate
- modulation scheme
- edge detection
- multiscale