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Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology.

Aibin YanZhengfeng HuangMaoxiang YiXiumin XuYiming OuyangHuaguo Liang
Published in: IEEE Trans. Very Large Scale Integr. Syst. (2017)
Keyphrases
  • cmos technology
  • low power
  • power consumption
  • power dissipation
  • case study
  • high speed
  • single chip
  • low voltage
  • mixed signal
  • user interface
  • image analysis
  • spl times
  • cmos image sensor