Verification of timed circuits with symbolic delays.
Robert ClarisóJordi CortadellaPublished in: ASP-DAC (2004)
Keyphrases
- asynchronous circuits
- model checking
- petri net
- colored petri nets
- timed automata
- verification method
- delay insensitive
- formal verification
- connectionist systems
- high level synthesis
- vlsi circuits
- high speed
- high level
- genetic algorithm
- digital circuits
- logic circuits
- formal methods
- symbolic representation
- finite state machines
- round trip
- lateral inhibition
- databases