Gate Stack Resistance and Limits to CMOS Logic Performance.
Richard A. WachnikSungjae LeeLi-Hong PanHongmei LiNing LuJing WangChristophe BernicotRaphael BingertMai RandallScott K. SpringerChristopher S. PutnamPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2014)
Keyphrases
- delay insensitive
- cmos technology
- high speed
- low cost
- chip design
- random access memory
- nm technology
- power consumption
- asynchronous circuits
- modal logic
- low power
- logic programming
- set theory
- gate dielectrics
- vlsi circuits
- natural deduction
- classical logic
- multi valued
- automated reasoning
- dynamic logic
- predicate logic
- proof theory
- field effect transistors
- digital circuits
- power supply
- circuit design
- floating gate