Login / Signup

Gate Stack Resistance and Limits to CMOS Logic Performance.

Richard A. WachnikSungjae LeeLi-Hong PanHongmei LiNing LuJing WangChristophe BernicotRaphael BingertMai RandallScott K. SpringerChristopher S. Putnam
Published in: IEEE Trans. Circuits Syst. I Regul. Pap. (2014)
Keyphrases