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Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.
Enrico Macii
Letícia Maria Veiras Bolzani
Andrea Calimera
Alberto Macii
Massimo Poncino
Published in:
DSD (2008)
Keyphrases
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power consumption
clock gating
power dissipation
power reduction
low power
energy efficiency
power saving
power management
computational power
circuit design
cmos technology
high speed
mixed signal
wireless networks
vlsi circuits