An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope.
Angxiao YanWei DengHaikun JiaShiyan SunChao TangBufan ZhuYu FuHongzhuo LiuBaoyong ChiPublished in: VLSI Technology and Circuits (2023)
Keyphrases
- clock frequency
- dielectric constant
- fourier transform
- instantaneous frequency
- power consumption
- high speed
- fractional fourier transform
- space variant
- frequency domain
- simulation software
- frequency band
- electric field
- moving target
- low frequency
- digital straight line
- real time
- root mean square
- parallel computing
- parallel architecture
- cmos technology
- frequency modulation
- object tracking
- error rate
- high end
- low power
- appearance model
- video streaming
- multi component
- spatial domain
- kalman filter
- dual band
- particle filter
- feature vectors