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A pixel pipeline architecture with selective z-test scheme for 3D graphics processors.

Jin-Hong ParkIl-San KimWoo-Chan ParkYong-Jin ParkTack-Don Han
Published in: Microprocess. Microsystems (2013)
Keyphrases
  • pipeline architecture
  • hardware implementation
  • test data
  • data sets
  • multiresolution
  • test cases
  • power consumption
  • pixel values
  • shared memory
  • pixel wise