Analog circuit verification by statistical model checking.
Ying-Chih WangAnvesh KomuravelliPaolo ZulianiEdmund M. ClarkePublished in: ASP-DAC (2011)
Keyphrases
- model checking
- analog circuits
- temporal logic
- model checker
- formal verification
- verification method
- automated verification
- temporal properties
- formal specification
- finite state machines
- finite state
- partial order reduction
- concurrent systems
- fault diagnosis
- process algebra
- formal methods
- digital circuits
- reachability analysis
- epistemic logic
- symbolic model checking
- transition systems
- bounded model checking
- asynchronous circuits
- pspace complete
- computation tree logic
- neural network
- reactive systems
- timed automata
- model based diagnosis
- deterministic finite automaton