A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations.
Chris H. KimJae-Joon KimSaibal MukhopadhyayKaushik RoyPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2005)
Keyphrases
- cmos technology
- power consumption
- semiconductor devices
- multithreading
- power reduction
- high speed
- real time
- management system
- sigma delta
- software architecture
- low power
- memory hierarchy
- query processing
- analog vlsi
- human body
- memory access
- low voltage
- caching scheme
- circuit design
- random access memory
- processing units
- low cost
- dynamic random access memory