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A new floating-point adder FPGA-based implementation using RN-coding of numbers.
Túlio Araujo
Matheus B. R. Cardoso
Erivelton G. Nepomuceno
Carlos H. Llanos
Janier Arias-Garcia
Published in:
Comput. Electr. Eng. (2021)
Keyphrases
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floating point
instruction set
fixed point
coding scheme
hardware architecture
hardware implementation
square root
application specific
scheduling problem
power consumption
fast fourier transform
sparse matrices
hardware architectures
floating point arithmetic