16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking.
Sudhir S. KudvaMahmut Ersin SinangilStephen G. TellNikola NedovicSanquan SongBrian ZimmerC. Thomas GrayPublished in: ISSCC (2024)
Keyphrases
- low power
- high density
- nm technology
- high power
- power consumption
- high speed
- low cost
- power reduction
- magnetic tape
- data center
- low density
- cmos technology
- power dissipation
- low power consumption
- logic circuits
- vlsi architecture
- single chip
- digital signal processing
- image sensor
- vlsi circuits
- ofdm system
- query processing
- computer simulation
- ultra low power