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Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization.
Xin-Wei Shih
Chung-Chun Cheng
Yuan-Kai Ho
Yao-Wen Chang
Published in:
ASP-DAC (2010)
Keyphrases
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high speed
power consumption
wide range
tree structure
duty cycle
objective function
response time
program synthesis
real time
bayesian networks
machine learning
data mining
multi dimensional
index structure
neural network
data sets
b tree
prefetching