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A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis.

Rie SoejimaKoji OkinaKeisuke DohiYuichiro ShibataKiyoshi Oguri
Published in: SIGARCH Comput. Archit. News (2014)
Keyphrases
  • high level synthesis
  • low cost
  • graph cuts
  • real world
  • artificial intelligence
  • information systems
  • image processing
  • user interface
  • high speed
  • power consumption
  • parallel processing