A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip.
Ramchan WooChi Weon YoonJeonghoon KookSe-Joong LeeHoi-Jun YooPublished in: IEEE J. Solid State Circuits (2002)
Keyphrases
- embedded dram
- high speed
- random access memory
- cmos technology
- power consumption
- low power
- dynamic random access memory
- low cost
- metal oxide semiconductor
- design considerations
- hardware implementation
- real time
- low voltage
- memory subsystem
- memory access
- general purpose
- field programmable gate array
- macroblock
- database systems