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A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC.
Taeho Seong
Yongsun Lee
Seyeon Yoo
Jaehyouk Choi
Published in:
ISSCC (2018)
Keyphrases
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error correction
low power
mixed signal
power consumption
low cost
high speed
low density parity check
single chip
error detection
data hiding
vlsi architecture
ldpc codes
channel coding
low power consumption
image sensor
logic circuits
watermarking scheme
multi channel
turbo codes