A process-tolerant low-power adder architecture for image processing applications.

Bharat Garg G. K. Sharma

Published in: Turkish J. Electr. Eng. Comput. Sci. (2019)

Keyphrases

low power
image processing
low cost
high speed
power consumption
logic circuits
vlsi architecture
data flow
real time
vlsi circuits
digital signal processing
single chip
cmos technology
machine vision
high power
computer vision
power dissipation
pattern recognition
delay insensitive