Layout Techniques for Minimizing On-Chip Interconnect Self Inductance.

Yehia Massoud Steve S. Majors Tareq Bustami Jacob White

Published in: DAC (1998)

Keyphrases

high speed
power dissipation
low cost
high density
analog vlsi
low power
real time
power consumption
end to end
physical design
data sets
image processing
genetic algorithm
transmission line
programmable logic
layout design
modular design
database
solid models
functional verification
ibm eservertm