C
search
search
reviewers
reviewers
feeds
feeds
assignments
assignments
settings
logout
Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips.
Donghyuk Lee
Samira Manabi Khan
Lavanya Subramanian
Rachata Ausavarungnirun
Gennady Pekhimenko
Vivek Seshadri
Saugata Ghose
Onur Mutlu
Published in:
CoRR (2016)
Keyphrases
</>
high density
main memory
response time
design process
low latency
high speed
quality of service
memory subsystem
case study
dynamic random access memory