A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O.
Kazuyuki NakamuraKoichi TakedaHideo ToyoshimaKenji NodaHiroaki OhkuboTetsuya UchidaToshiyuki ShimizuToshiro ItaniKen TokashikiKoji KishimotoPublished in: IEEE J. Solid State Circuits (1997)
Keyphrases
- noise reduction
- cmos technology
- power consumption
- random access memory
- main memory
- high speed
- low power
- nm technology
- memory access
- hard disk
- signal to noise ratio
- silicon on insulator
- inter frame
- edge preserving
- low voltage
- gigabit ethernet
- cache misses
- coding scheme
- flash memory
- edge detection
- replacement policy
- input output
- noisy environments
- noise removal
- disk array
- database workloads
- buffer pool
- noise level
- edge enhancement
- median filter
- wiener filter
- noise free
- external memory
- data access
- block size
- data transmission
- hearing aids
- low cost
- prefetching
- speech enhancement
- image sensor
- index structure
- power dissipation
- noise detection
- shared memory
- solid state