Reducing Garbled Circuit Size While Preserving Circuit Gate Privacy.

Yongge Wang Qutaibah M. Malluhi

Published in: IACR Cryptol. ePrint Arch. (2017)

Keyphrases

cmos technology
high speed
circuit design
analog circuits
multiple input
electronic circuits
tunnel diode
privacy preserving
logic circuits
low power
power reduction
delay insensitive
short circuit
gallium arsenide