A Low Power Deterministic Test Using Scan Chain Disable Technique.
Zhiqiang YouTsuyoshi IwagakiMichiko InoueHideo FujiwaraPublished in: IEICE Trans. Inf. Syst. (2006)
Keyphrases
- low power
- power consumption
- low cost
- high speed
- single chip
- high power
- wireless transmission
- vlsi circuits
- logic circuits
- vlsi architecture
- low power consumption
- cmos technology
- mixed signal
- power reduction
- digital signal processing
- image sensor
- image processing
- signal processor
- gate array
- delay insensitive
- power saving
- video sequences