A linear model for high-level delay estimation in VDSM on-chip interconnects.
Alberto García OrtizTudor MurganMihail PetrovManfred GlesnerPublished in: ISCAS (2) (2005)
Keyphrases
- linear model
- high level
- power dissipation
- semi parametric
- least squares
- regression model
- low level
- power consumption
- linear models
- high speed
- regression trees
- low power
- nonlinear models
- input output
- parameter estimation
- low cost
- additive model
- high density
- linear transformations
- linear transformation
- phase locked loop
- face recognition