A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.
Il-Min YiSeung-Jun BaeMin-Kyun ChaeSoo-Min LeeYoung Jae JangYoung-Chul ChoYoung-Soo SohnJung-Hwan ChoiSeong-Jin JangByungsub KimJae-Yoon SimHong-June ParkPublished in: VLSI Circuits (2016)