Optimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some Insights and Explanations.
Kuntal RoyPublished in: J. Comput. Inf. Technol. (2007)
Keyphrases
- logic circuits
- delay insensitive
- low power
- cmos technology
- multi valued
- high speed
- power dissipation
- nm technology
- power consumption
- asynchronous circuits
- low cost
- logic programming
- predicate logic
- differential equations
- chip design
- nano scale
- gate dielectrics
- power supply
- neural network
- classical logic
- shortest path
- global optimum
- analog vlsi
- data mining
- modal logic
- low voltage
- single chip
- optimal path
- real time
- vlsi circuits
- partial order
- floating gate
- flip flops
- automated reasoning
- leakage current
- minimum cost path
- image sensor