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SAT-based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions.
Satoshi Jo
Takeshi Matsumoto
Masahiro Fujita
Published in:
IPSJ Trans. Syst. LSI Des. Methodol. (2014)
Keyphrases
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asynchronous circuits
semi automatic
answer set programming
logic circuits
high speed
logic programming
sat solvers
analog circuits
bounded model checking
stereo images
software testing
delay insensitive
hardware designs