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A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance.

Sylvain ClercFady AbouzeidGilles GasiotDavid GauthierDimitri SoussanPhilippe Roche
Published in: ICICDT (2012)
Keyphrases
  • random access memory
  • power consumption
  • error tolerance
  • low voltage
  • nm technology
  • design considerations
  • memory access
  • cmos technology
  • low cost
  • low power
  • learning algorithm
  • high speed
  • x ray