Fixed latency on-chip interconnect for hardware spiking neural network architectures.
Sandeep PandeFearghal MorganGerard J. M. SmitTom M. BruintjesJochem H. RutgersBrian McGinleySeamus CawleyJim HarkinLiam McDaidPublished in: Parallel Comput. (2013)
Keyphrases
- high speed
- low latency
- clock frequency
- low cost
- vlsi implementation
- power consumption
- programmable logic
- evolvable hardware
- circuit design
- bio inspired
- memory bandwidth
- high bandwidth
- single chip
- field programmable gate array
- low power
- host computer
- real time
- hardware and software
- chip design
- heterogeneous computing
- ibm zenterprise
- power dissipation
- ibm power processor
- level parallelism
- high end
- image sensor
- processor core
- input output
- parallel architecture
- embedded systems
- feed forward
- content addressable memory
- basal ganglia
- multithreading
- response time
- commodity hardware
- single neuron
- neuron model
- hebbian learning
- cmos technology
- resource utilization
- hardware implementation
- prefetching
- signal processor
- artificial neural networks