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Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology.
Debabrata Ghosh
S. K. Nandy
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (1995)
Keyphrases
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cmos technology
low power
power dissipation
design process
case study
low cost
power consumption
computer architecture
low voltage