Partial Row Activation for Low-Power DRAM System.
Yebin LeeHyeonggyu KimSeokin HongSoontae KimPublished in: HPCA (2017)
Keyphrases
- low power
- power consumption
- high speed
- low cost
- cmos technology
- single chip
- high power
- logic circuits
- high density
- image sensor
- vlsi architecture
- vlsi circuits
- low voltage
- digital signal processing
- main memory
- wireless transmission
- gate array
- power saving
- low power consumption
- digital camera
- real time
- ultra low power
- signal processor
- power management
- power dissipation