A Non-Blocking Multistage Interconnection using Regular Clock Schemes for QCA Circuits.
Stefan T. Couperus LealMichael CanescheOmar P. Vilela NetoRicardo S. FerreiraJosé A. M. NacifPublished in: SBCCI (2023)
Keyphrases
- multistage
- high speed
- power consumption
- power dissipation
- cmos technology
- cellular automata
- dynamic programming
- single stage
- lot sizing
- stochastic programming
- low power
- production system
- stochastic optimization
- production line
- optimal policy
- reinforcement learning
- high density
- record linkage
- low cost
- capacity expansion
- lot streaming