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A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment.
Hong-Sik Kim
Sungho Kang
Michael S. Hsiao
Published in:
J. Electron. Test. (2008)
Keyphrases
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low power
power consumption
low cost
vlsi architecture
real time
high speed
test cases
hardware and software
high power
hardware software co design
signal processing
compression ratio
computing systems
single chip
cmos technology
low power consumption