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A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate.
Vandana Shukla
O. P. Singh
G. R. Mishra
R. K. Tiwari
Published in:
Int. J. Bus. Data Commun. Netw. (2015)
Keyphrases
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digital circuits
case study
circuit design
logic synthesis
multi valued
logic circuits
micron cmos
high speed
design process
chip design
neural network
markov chain
classical logic
evolvable hardware
binary representation
delay insensitive