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An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM.

Weichen TaoWeichen ZhaoRobert Bogdan StaszewskiFujiang LinYizhe Hu
Published in: VLSI Technology and Circuits (2023)
Keyphrases
  • user friendly
  • phase locked loop
  • feature selection
  • high speed
  • packet loss
  • root mean square
  • database
  • steady state
  • multiscale
  • end to end
  • imbalanced data
  • sampling procedure
  • charge coupled devices