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10-315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation.

Minyoung SongYoung-Ho KwakSunghoon AhnHojin ParkChulwoo Kim
Published in: IEEE Trans. Very Large Scale Integr. Syst. (2013)
Keyphrases
  • high speed
  • phase locked loop
  • power consumption
  • real time
  • multiresolution
  • face detection
  • high frequency
  • fpga device