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How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance.
Dries Vercruyce
Elias Vansteenkiste
Dirk Stroobandt
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2018)
Keyphrases
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circuit design
design automation
digital circuits
real time
genetic algorithm
high speed
field programmable gate array
neural network
hierarchical structure
lower level
hardware design
real time image processing
hierarchically organized
verilog hdl