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A Synchronous 50% Duty-Cycle Clock Generator in 0.35- μ m CMOS.
Tsung-Hsien Lin
Chao-Ching Chi
Wei-Hao Chiu
Yu-Hsiang Huang
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2011)
Keyphrases
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duty cycle
real time
high speed
low cost
power consumption
low power
clock frequency
analog vlsi
image processing
circuit design
information systems
general purpose
response time
signal processing
image sensor
cmos technology