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Efficient hardware architecture for integer implementation of multi-alphabet arithmetic coding for data mining.
S. D. Jayavathi
A. Shenbagavalli
B. Ganapathy Ram
Published in:
Int. J. Bus. Intell. Data Min. (2018)
Keyphrases
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hardware architecture
hardware implementation
hardware architectures
arithmetic coding
efficient implementation
image compression
machine learning
computer vision
data structure
pairwise
high order
compression algorithm
associative memory
field programmable gate array