S. D. Jayavathi

Publication Activity (10 Years)

Years Active: 2018-2019
Publications (10 Years): 2

Top Topics

Arithmetic Coding

Image Compression

Hardware Implementation

Top Venues

Int. J. Bus. Intell. Data Min.

J. Real Time Image Process.

Publications

S. D. Jayavathi, A. Shenbagavalli
FPGA-based Auxiliary Minutest MQ-coder architecture of JPEG2000. J. Real Time Image Process. 16 (5) (2019)
S. D. Jayavathi, A. Shenbagavalli, B. Ganapathy Ram
Efficient hardware architecture for integer implementation of multi-alphabet arithmetic coding for data mining. Int. J. Bus. Intell. Data Min. 13 (1/2/3) (2018)