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Robust activating timing for SRAM SA with replica cell voltage boosted circuit.

Zhengping LiMingming XieXincun JiYongliang Zhou
Published in: IEICE Electron. Express (2016)
Keyphrases
  • low voltage
  • simulated annealing
  • high speed
  • computationally efficient
  • duty cycle
  • power consumption
  • real time
  • neural network
  • asynchronous circuits
  • analog vlsi