An optically-enabled chip-multiprocessor architecture using a single-level shared optical cache memory.
Pavlos ManiotisSavvas GitzenisLeandros TassiulasNikos PlerosPublished in: Opt. Switch. Netw. (2016)
Keyphrases
- multiprocessor architecture
- memory subsystem
- memory access
- multithreading
- processor core
- memory hierarchy
- production system
- main memory
- speculative execution
- memory bandwidth
- cache misses
- data access
- shared memory multiprocessors
- dynamic random access memory
- distributed shared memory
- random access memory
- instruction set
- shared memory
- cache conscious
- operating system
- printed circuit boards
- processing units
- virtual memory
- ibm zenterprise
- low cost
- memory management
- secondary storage
- external memory
- level parallelism
- solid state
- garbage collection
- image sensor
- index structure
- query processing
- fiber optic
- multistage
- memory requirements
- floating point
- parallel computing
- access patterns
- high density