Reducing Off-Chip Miss Penalty by Exploiting Underutilised On-Chip Router Buffers.

Abhijit Das Abhishek Kumar John Jose

Published in: ICCD (2020)

Keyphrases

high speed
low cost
network on chip
analog vlsi
high density
programmable logic
single chip
physical design
objective function
solid models
cmos technology
end to end
input output
cmos image sensor
circuit design
power dissipation
dynamic range
genetic algorithm
ibm power processor